Method of manufacturing a trench gate type field effect transistor

ABSTRACT

A trench gate type field effect transistor capable of effectively suppressing the short channel effect is formed with a shallow junction between a source and a drain, at low resistance, and through a simple process. In a method of manufacturing a trench gate type field effect transistor ( 100 A), wherein an impurity introduced layer ( 13 ) which is to become a source or a drain is formed by introducing an impurity into a semiconductor substrate ( 1 ), a trench ( 15 ) is formed in the impurity introduced layer, a gate insulating film ( 5 ) is formed on a bottom face of the trench ( 15 ), and a gate (G) is formed so as to fill the trench ( 15 ), laser annealing for activating the impurity is performed after the impurity is introduced into the semiconductor substrate ( 1 ) and before the gate G is formed.

BACKGROUND OF THE INVENTION

The present invention relates to a method of manufacturing a trench gatetype field effect transistor which accommodates miniaturization.

MOS type LSIs using silicon substrates are currently in a phase whereLSIs with a 0.18-μm design rule (design criterion) have shifted intomass production, but further improvements in the degree of integration,through miniaturization, are desired, and LSIs with 0.13-μm to 0.10-μmdesign rules are under development. Higher operating speeds and lowerpower consumption are also desired in these LSIs.

When an LSI is miniaturized and the degree of integration is made largerin scale, suppressing the short channel effect becomes an extremelyimportant issue in reducing deviations in the performance of theindividual transistors.

To suppress the short channel effect, in MOS type field effecttransistors which are already put to practical use and in which a gateis formed on a semiconductor substrate, and a source and a drain areformed in a self-aligned manner with respect to the gate, attempts tooptimize the impurity concentrations or shapes of the source and thedrain, well impurity profiles in a channel area and the like are beingmade, and further, forming an impurity area, commonly referred to as ahalo or a pocket, of an opposite conductivity type at an end of thesource or the drain through methods such as oblique ion implantation orthe like, and suppressing the short channel effect are being attempted.

In addition, for the suppression of the short channel effect, formingthe source and the drain shallow while maintaining the low resistivitiesof the source and the drain becomes a fundamental and important factor.

Conventionally, the activation of impurities introduced into asemiconductor substrate to form a source and a drain is performedthrough a thermal treatment (900 to 950° C., 20 to 30 minutes) using aresistance heating furnace. In recent years, however, in order to formthe source and the drain shallow and low in resistance by preventingimpurity diffusion due to this thermal treatment, RTA (Rapid ThermalAnnealing) using a halogen lamp is being performed.

In FIG. 3, a typical temperature increase-decrease profile of RTA isshown. In RTA, it rises to an annealing temperature of 1000 to 1100° C.at a rate of rise in temperature of 50 to 100° C., this annealingtemperature is maintained for approximately 10 seconds, and naturalcooling is performed.

In FIG. 4A to FIG. 4H, a method of manufacturing a typical n-type fieldeffect transistor 100X, in which junctions of a source and a drain areformed using RTA, is shown. In this method, first, element separators 2are formed in a p-type silicon substrate 1, and a through-film 3comprising SiO₂ or the like is formed (FIG. 4A), and ions are implantedas per the arrows through the through-film 3 to form a well 4 and aV_(th) adjusting layer (not shown) (FIG. 4B). Next, the through-film 3is removed, and a gate insulating film 5 of approximately 3 to 5 nm isformed through thermal oxidation of 1000° C. and approximately 30minutes. A polysilicon 6 with a thickness of approximately 500 nm anddoped with phosphorus at a high concentration is deposited thereonthrough low-pressure CVD or the like. Approximately 300 nm of WSi 7 isdeposited thereon through the CVD method to reduce gate resistance (FIG.4C).

Then, a gate pattern with a desired design rule is formed usinglithography technology and etching technology. With this gate pattern asa mask, approximately 1×10¹⁵ cm⁻² of impurities such as arsenic, whichbecome an extended source 8 a and an extended drain 8 b, are ionimplanted at 10 keV as per the arrows (FIG. 4D). Next, an SiO₂ film isdeposited by normal CVD and a side wall 9 is formed by performinganisotropic etching. By performing ion implantation again, approximately3×10¹⁵ cm⁻² of arsenic, which forms an impurity introduced layer whichis to become a source S and a drain D, is introduced at 30 keV (FIG.4E).

Next, in order to form a pocket (halo) 10 for suppressing the shortchannel effect, approximately 1×10¹³ cm⁻²of a p-type impurity ision-implanted at an angle of 10° to 30° with respect to the normal tothe substrate surface at 20 keV (FIG. 4F). Then, in order to activatethe impurities introduced into the substrate 1 up to this point,annealing of 1050° C. and approximately 10 seconds is performed by RTAusing a halogen lamp.

Thereafter, an interlayer insulating film 11 of SiO₂ or the like isdeposited with the CVD method (FIG. 4G). Next, lead electrodes 14 of thesource and the drain are formed in the interlayer insulating film 11 toobtain the transistor 100X (FIG. 4H).

However, even when RTA is used for the formation of the junctions of thesource and the drain as described above, because cooling through naturalradiation is performed after the annealing temperature has beenmaintained, the rate of fall in temperature during cooling cannot becontrolled, and the profile due to the diffusion of the impuritiesduring the fall in temperature presents a problem.

To this end, as shown in FIG. 5, methods such as spike RTA which takesthe maintaining time at the annealing temperature to be zero, or quickcooling RTA, in which He gas or the like is used to force cool duringthe fall in temperature, are adopted.

However, even when these methods are utilized fully, the depth of thejunctions and the resistance values of the source and the drain do notreach the values demanded of transistors with a gate length of 130 nm orbelow in the road map (ITRS '99) in the engineering community as shownin FIG. 6.

In addition, if RTA is performed when an impurity is introduced throughion implantation, point defects, such as numerous interstitial atoms orholes formed due to crystal damage from the impact of the ions, causeenhanced diffusion at the initial stage of the thermal treatment of RTA.Thus, while redistribution of the impurities due to normal thermaldiffusion is suppressed considerably, diffusion of the impuritiesaccompanying the enhanced diffusion of the point defects occurs, and theimpurity profile causes a significant redistribution.

As such, as an activation method for the impurities, annealing usingexcimer laser is being considered. In the annealing with excimer laser,since the temperature rises to 1000° C. or higher in an extremely shortperiod of time of several nanoseconds, the impurities can be activatedwithout any accompanying enhanced diffusion. In FIG. 7, the relationshipbetween the depth of junction, the surface resistivity (ohm/square) andthe laser energy density (mJ/cm²) of a p+ layer, in which BF₂ (15 KeVand 3×10¹⁵ cm⁻²) is implanted and which is activated with a XeCl excimerlaser (a wavelength of 308 nm and a pulse width of 40 nsec), is shown.

In the annealing with excimer laser, since heating is performed in anextremely short period of time, the annealing treatment is performed ina thermally nonequilibrium state. Therefore, as compared with the casewhere annealing is performed through RTA, forming a shallow andlow-resistance junction becomes possible as shown in FIG. 7. However,with the excimer laser, there are cases where a gate thermally insulatedfrom a semiconductor substrate by a gate insulating film reaches atemperature exceeding the melting point of the base material thereofduring annealing, and deformation or breakage is brought about due tomelting.

To address such a problem, a selective annealing method for performingthermal treatment only on desired sections such as a source and a drainis needed.

As a selective annealing method, there is a method in which, making useof the fact that the reflectance of a laser varies depending on thethickness of a Si oxide film, Si oxide films with different filmthicknesses are formed on a material to be irradiated depending on thepresence or absence of the necessity of a thermal treatment, and laseris irradiated. More specifically, for example, with respect to anexcimer laser of a wavelength of 308 nm, the reflectance of a Si oxidefilm shows changes with respect to the film thickness of the Si oxidefilm as shown in FIG. 8. Therefore, in the selective excimer laserannealing method using an excimer laser, an Si oxide film is depositedwith a film thickness of 50 nm, at which the reflectance is minimum, ona section in which thermal treatment is desired, and with a filmthickness of 100 nm, at which the reflectance is maximum, on a sectionin which thermal treatment is not desired (H. Tsukamoto et al, Jpn. J.Appl. Phys. 32, L967 (1993)).

In FIG. 9A to FIG. 9I, a method of manufacturing a conventional n-typetransistor, in which this selective excimer laser annealing method isused to activate impurities in a source and a drain, is shown. In thismethod, first, element separators 2 are formed in a p-type siliconsubstrate 1, a through-film 3 comprising SiO₂ or the like is formed(FIG. 9A), and ions are implanted through the through-film 3 to form awell 4 and a V_(th) adjusting layer (not shown) (FIG. 9B). Next, thethrough-film 3 is removed, approximately 3 to 5 nm through thermaloxidation of 1000° C. and approximately 30 minutes. Thereon, apolysilicon 6 of a thickness of approximately 500 nm and doped withphosphorous at a high concentration is deposited throughreduced-pressure CVD or the like. Approximately 300 nm of WSi 7 isdeposited thereon through the CVD method to reduce gate resistance, andfurther, an Si oxide film 12 a with a film thickness of 50 nm isdeposited through LPCVD or the like (FIG. 9C).

Then, lithography technology and etching technology are used to form agate pattern with a desired design rule (polysilicon 6/WSi 7/Si oxidefilm 12 a). Then, with this gate pattern as a mask, approximately 1×10¹⁵cm⁻² of impurities such as arsenic, which become an extended source 8 aand an extended drain 8 b, are ion-implanted at 10 keV as per the arrows(FIG. 9D). Next, a side wall 9 is formed by depositing a SiO₂ film witha normal CVD method and performing anisotropic etching. By implantingions again, approximately 3×10¹⁵ cm⁻² of arsenic which forms an impurityintroduced layer which is to become a source S and a drain D isintroduced at 30 keV (FIG. 9E).

Next, in order to form a pocket (halo) 10 for suppressing the shortchannel effect, approximately 1×10¹³ cm⁻² of a p-type impurity ision-implanted at an angle of 10° to 30° with respect to the normal tothe substrate surface at 20 keV (FIG. 9F).

Then, as an anti-reflection film, an Si oxide film 12 b is depositedwith the CVD method and in a film thickness of 50 nm, at which excimerlaser exhibits minimum reflectance. Thus, this Si oxide film 12 b of afilm thickness of 50 nm is formed on the impurity introduced layer whichis to become the source S and the drain D, and on the gate pattern, Sioxide films of a total film thickness, from this Si oxide film 12 b andthe Si oxide film 12 a deposited before the formation of the gatepattern, of 100 nm, in other words of a film thickness at which thereflectance of the excimer laser is maximum, are formed (FIG. 9G).

Next, to activate the impurities introduced into the substrate 1 up tothis point, annealing is performed at an energy density of 900 to 1000mJ/cm² using an excimer laser L (FIG. 9H).

Thereafter, an interlayer insulating film 11 of SiO₂ or the like isdeposited with the CVD method, and subsequently, lead electrodes 14 ofthe source and the drain are formed in the interlayer insulating film 11to obtain a transistor 100Y (FIG. 9I).

When the transistor 100Y is thus formed with the selective annealingmethod, because the source S and the drain D, of which the impuritiesshould be activated, alone are heated to a high temperature withouthaving the gate G heated to a high temperature, deformation or breakageof the gate G accompanying annealing can be prevented. In addition,since a thermally non-equilibrium laser annealing is performed in thesource S and the drain D, a shallow and low-resistance junction can beformed. Thus, according to this method, it is possible to form atransistor which operates with a gate length of 0.1 μm or below (H.Tsukamoto et al, Jpn. J. Appl. Phys. 32, L967 (1993)).

In this method, however, because selective laser annealing is performed,the addition and the difficulty of the step accompanies in that the Sioxide films 12 a and 12 b must be uniformly formed with predeterminedfilm thicknesses over the entire substrate surface before and after theformation of the gate pattern.

As described above, in the conventionally employed method using aresistance heating furnace or the method using RTA, in activating theimpurities introduced into the substrate to form the source or the drainof the field effect transistor, it is difficult to form junctions of thesource and the drain shallow and with low resistance to an extent thatthe short channel effect can be effectively suppressed in an extremelyminiaturized transistor with a gate length of 0.1 μm or below.

In addition, when the selective laser annealing method is used, althoughit is possible to form junctions of the source and the drain shallow andwith low resistance, the addition and the difficulty of the step areinvolved.

To this end, it is an object of the present invention to provide a newmethod of manufacturing a field effect transistor which forms anextremely miniaturized field effect transistor with junctions of asource and a drain shallow, with low resistance and with a simpleprocess to an extent that the short channel effect can be effectivelysuppressed.

SUMMARY OF THE INVENTION

The present inventor has found that the formation of the Si oxide film12 a which complicates the process in the conventional selective laserannealing method shown in FIG. 9A to FIG. 9I is required in order toperform laser annealing after the formation of the gate pattern, andtherefore that if laser annealing is applied to a trench gate type fieldeffect transistor, in which annealing is performed before the formationof the gate pattern, the step for forming the Si oxide film 12 a can beomitted.

In other words, the present invention provides, in a method ofmanufacturing a trench gate type field effect transistor in which animpurity introduced layer, which is to become a source or a drain, isformed by introducing an impurity into a semiconductor substrate,

a trench is formed in the impurity introduced layer,

a gate insulating film is formed on a bottom face of the trench, and

a gate is formed so as to fill the trench,

a method of manufacturing a trench gate type field effect transistorcharacterized in that laser annealing for activating the impurity isperformed after the impurity is introduced into the semiconductorsubstrate and before the gate is formed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A to FIG. 1I are explanatory views of the steps for a method ofmanufacturing a transistor of an embodiment;

FIG. 2A to FIG. 2J are explanatory views of the steps for a method ofmanufacturing a transistor in of embodiment;

FIG. 3 is a temperature increase-decrease profile of RTA;

FIG. 4A to FIG. 4H are explanatory views of the steps for a method ofmanufacturing a conventional n-type transistor;

FIG. 5 is temperature increase-decrease profiles in spike RTA and quickcooling RTA;

FIG. 6 is a diagram of the relationship between the junction depth andthe surface resistivity of a p-n junction formed using spike RTA andquick cooling RTA;

FIG. 7 is a diagram of the relationship between junction depth, surfaceresistivity, and laser energy density in excimer laser annealing;

FIG. 8 is a diagram of the relationship between the film thickness andthe reflectance of an excimer laser with respect to a Si oxide film;

FIG. 9A to FIG. 9I are explanatory views of the steps for a method ofmanufacturing a transistor using a conventional selective laserannealing method.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

The present invention is hereinafter described in specific terms withreference to the drawings. In the respective drawings, the samereference numerals represent the same or equivalent elements.

FIG. 1A to FIG. 1I are explanatory views of the steps in an embodimentof a manufacturing method of the present invention for forming an n-typetrench gate type MOS (MIS) transistor with an effective gate length ofapproximately 0.1 μm.

In the present embodiment, element separators 2 such as shallow trenchesare formed in a p-type silicon substrate 1, further, a through-film 3comprising SiO₂ or the like is formed, and ions are implanted throughthe through-film 3 as per the arrows to form a well 4 and a V_(th)adjusting layer (not shown) (FIG. 1A).

Next, approximately 5×10¹⁵ cm⁻² of phosphorus, arsenic or the like,which are n-type impurities, is ion-implanted to a depth ofapproximately 40 nm as per the arrows to form an impurity introducedlayer 13, which is to form a source S and a drain D (FIG. 1B). Inaddition, in order to form an impurity introduced layer 8 correspondingto the extended sources 8 a and the extended drains 8 b of theconventional type transistors shown in FIG. 4A to FIG. 4H and FIG. 9A toFIG. 9I, approximately 1×10¹⁵ cm⁻²of an n-type impurity is implanted ata depth approximately 20 nm deeper than the impurity introduced layer13, which is to form the source S and the drain D (FIG. 1C).

Next, a Si oxide film 12 with a thickness of approximately 50 nm isformed as an anti-reflection film for effectively making an excimerlaser be absorbed (FIG. 1D). For this Si oxide film 12, the through-film3 already formed may be thinned to approximately 50 nm through etchingor the like, or an Si oxide film with a film thickness of approximately50 nm may be re-deposited anew.

Thereafter, to activate the impurities introduced into the substrate 1up to this point, laser annealing, in which a XeCl excimer laser L witha wavelength of 308 nm is irradiated at an energy density ofapproximately 900 mJ/cm², is performed (FIG. 1E).

Next, approximately 0.2 to 0.3 μm of an interlayer insulating film 11 ofSi₃N₄, SiO₂ or the like is deposited through the CVD method, andsubsequently, lithography technology using a KrF laser and dry etchingtechnology are used to form a trench 15, which is to form a gate in acenter portion of an area sandwiched between the element separators 2,with a width W of 0.1 μm, penetrating the interlayer insulating film 11and down to a position deeper than the end of the profile of theimpurity introduced layer 8 corresponding to an extended source 8 a andan extended drain 8 b by several ten nanometers (FIG. 1F).

Then, by performing thermal oxidation in dry oxygen of 900° C. andapproximately 20 minutes, a gate insulating film 5 comprising an oxidefilm with a thickness of approximately 2 to 3 nm is grown on the bottomface and the side face of the trench 15 (FIG. 1G). As the gateinsulating film 5, a high permittivity insulating film of Al₂O₃ or thelike may be formed through sputtering or CVD.

Next, a gate electrode material 16 such as polysilicon/tungstensilicide, or TiN, Mo or the like which becomes a metal gate is filledinside the trench 15 with the CVD method or the sputtering method, andplanarization is performed through CMP or the like to form a gate G(FIG. 1H).

Finally, by opening holes in the interlayer insulating film 11, blankettungsten or the like is embedded therein, and by removing the excesstungsten by etching back, CMP or the like, lead electrodes 14 of thesource S and the drain D are formed to obtain a trench gate typetransistor 100A (FIG. 1I).

When the trench gate type transistor 100A is formed in this manner,because the activation of the impurities of the source S, the drain Dand others is performed before the formation of the gate, it is possibleto form junctions of the source S and the drain D at an extremelyshallow depth of approximately 50 nm with a low resistance ofapproximately 200 ohms/square. In addition, according to this method ofmanufacture, since it is unnecessary to form Si oxide films of differentfilm thicknesses on the source S, the drain D and the gate G which areconventionally required for selectively performing laser annealing, thetransistor manufacturing process can be simplified as compared with theconventional selective laser annealing method. Furthermore, a trenchgate type transistor has an advantage in that the short channel effectis structurally less likely to occur since the range between the sourceS and the drain D is larger than the gate length, and the source S doesnot directly face the drain D. According to the method of the presentembodiment, such a trench gate type transistor can be formed with ease.

FIG. 2A to FIG. 2J are explanatory views of the steps of a differentaspect of the present invention for manufacturing a trench gate type MOS(MIS) transistor 100B in which the capacitance between a source, a drainand a gate is lower than that of the transistor 100A shown in FIG. 1A toFIG. 1I.

In the present embodiment, as with the transistor 100A shown in FIG. 1Ato FIG. 1I, element separators 2, a through-film 3, a well 4, and aV_(th) adjusting layer (not shown) are formed in a p-type siliconsubstrate 1 (FIG. 2A). An impurity introduced layer 13 for forming asource S and a drain D (FIG. 2B), and, as an anti-reflection film, an Sioxide film 12 with a thickness of approximately 50 nm, for effectivelyhaving an excimer laser be absorbed, are formed (FIG. 2C), and laserannealing is performed (FIG. 2D).

Next, approximately 0.4 to 0.5 μm of an interlayer insulating film 11 ofSi₃N₄, SiO₂ or the like is deposited by the CVD method or the like, andlithography technology using KrF laser and dry etching technology areused to form a first trench 20 in a center portion of an area sandwichedbetween the element separators 2 with a width W of 0.18 μm, penetratingthe interlayer insulating film 11, and at a position shallower than theend of the profile of the impurity introduced layer 13, which is to formthe source S and the drain D, by approximately 10 nm (FIG. 2E).

Next, the CVD method is combined with anisotropic etching to form a sidewall 21 comprising an insulating material such as SiO₂ on the side wallof the first trench 20 with a thickness W2 of approximately 0.05 μm, andthe substrate 1 is exposed at the bottom face of the first trench 20(FIG. 2F).

By performing selective etching on the substrate 1 exposed at the bottomface of the first trench 20 with the side wall 21 as a mask, a secondtrench 22 is formed down to the depth of the end of the profile of theimpurity introduced layer 13 or to a depth deeper than the end byapproximately several nanometers (FIG. 2G).

Next, a gate insulating film 5 with a thickness of 2 to 3 nm is formedby thermally oxidizing the bottom face of the second trench 22 in dryoxygen of 950° C. and 20 minutes. Alternatively, a gate insulating film5 comprising a high permittivity insulating material, such as Al₂O₃, isformed using the sputtering method, the normal CVD method, an atomiclayer chemical vapor deposition method or the like (FIG. 2H).

Then, a gate electrode material 16 such as polysilicon/tungstensilicide, or TiN and Mo, which become a metal gate, is filled inside thetrench by the CVD method or the sputtering method, and is planarizedthrough CMP or the like (FIG. 2I).

Finally, as with the transistor 100A in FIG. 1A to FIG. 1I, leadelectrodes 14 of the source S and the drain D are formed to obtain thetransistor 200B (FIG. 2J).

When the trench gate type transistor 100B is formed in this manner, aswith the trench gate type transistor 100A in FIG. 1A to FIG. 1I, laserannealing is performed with a simplified process as compared to theconventional selective laser annealing method, and a transistor with lowresistance and in which the junctions of the source S and the drain Dare extremely shallow can be obtained.

Further, according to this manufacturing method for the trench gate typetransistor 100B, since the the source S or the drain D and the gate Gare separated by the side wall 21, the capacitance between the source Sor the drain D and the gate G can be reduced significantly. Thiscapacitance reducing effect is further effective since the extremelyshallow source S and drain D are formed.

In addition, because the second trench 22 is formed with the side wall21 in a self-aligned manner with respect to the first trench 20, and awidth W3 of the second trench 22 is formed narrower than the width W1 ofthe first trench 20, the width W3 of the second trench 22 isautomatically formed with a width narrower than the lithographycapabilities which define the first trench 20. More specifically, forexample, when the width W1 of the first trench 20 is taken to be 0.18 μmand the width W2 of the side wall 21 is taken to be 0.05 μm, it followsthat the width W3 of the second trench 22 will be formed to be 0.08 μm.Thus, according to the present embodiment, it becomes possible to form aminiaturized transistor with an extremely short gate length of 0.08 μmor below, which is considered difficult even with KrF lithographycurrently used in practice.

In the formation of the trench gate type transistor 100B having thefirst and second trenches and shown in FIG. 2A to FIG. 2J, as with thetrench gate type transistor 100A shown in FIG. 1A to FIG. 1I, animpurity introduced layer corresponding to an extended source and anextended drain may also be formed. In such a case, laser annealing isperformed after the impurity introduced layer corresponding to theextended source and the extended drain is formed in the substrate, andthereafter, the first trench is formed.

Alternatively, the impurity introduced layer corresponding to theextended source and the extended drain is formed after the formation ofthe first trench 20, and thereafter, laser annealing is performed. Inthis case, the thickness of the interlayer insulating film 11 is formedthinner than in the case shown in FIG. 2A to FIG. 2J so that sufficientabsorption of the laser is performed. After the laser annealing, as inthe method shown in FIG. 2A to FIG. 2J, the side wall is formed, thesecond trench is formed, the gate insulating film is formed in thesecond trench, and these trenches are filled with the gate metalmaterial to form the transistor.

The present invention can take various modes other than these. Forexample, while in the aforementioned embodiments, an example in which aXeCl excimer laser with a wavelength of 308 nm is used is indicated,excimer lasers such as KrF and ArF may also be used. Further, as long asit can be irradiated with a suitable energy density, it is not limitedto excimer lasers, and other lasers may also be used.

In addition, while in the aforementioned embodiments, manufacturingmethods for n-type MOS or MIS transistors are described, by reversingthe conductivity types of the substrate and the impurities, it canlikewise be applied to p-type transistors as well.

The metals used as the material for forming the gate or thehigh-permittivity insulating film used as the gate insulating film arealso not limited to the aforementioned examples. It is possible toselect, as deemed appropriate, materials which are stable materials andhave good moldability and which are metals with proper work functions orhigh-permittivity insulating materials with a proper band gap.

The thicknesses of the various films, the impurity concentrations, thedepths of the impurity layers and the like, too, are not limited to theaforementioned examples, and can be optimized depending on the gatelength, V_(th), the current driving capability, and other desiredcharacteristics of the transistor to be formed.

According to the present invention, since the activation of theimpurities which are to form the source, the drain or the like isperformed through laser annealing in the manufacturing process for thetrench gate type transistor, it is possible to form an extremelyminiaturized trench gate type transistor having a gate length of 0.1 μmor below with the extremely shallow junctions of the source and thedrain and with low resistance, and through a simplified process. Byvirtue of the fact that the junction between the source and the draincan be formed extremely shallow, the capacitance between the source orthe drain and the gate can be significantly reduced.

In addition, according to the present invention, by virtue of the factthat the junction between the source and the drain can be formedextremely shallow, it becomes possible to form the trench, in which thegate is embedded, itself shallow, and deviations in the effective gatelength due to deviations in the processing accuracy of etching and thelike can be reduced. Thus, reductions in deviations of drain currents orV_(th) are facilitated.

1. In a method of manufacturing a trench gate type field effecttransistor wherein an impurity introduced layer, which becomes a sourceor a drain, is formed by introducing an impurity into a semiconductorsubstrate, a trench is formed in the impurity introduced layer, a gateinsulating film is formed on a bottom face of the trench, and a gate isformed so as to fill the trench, a method of manufacturing a trench gatetype field effect transistor characterized in that laser annealing foractivating the impurity is performed after the impurity is introducedinto the semiconductor substrate and before the gate is formed, whereina flat anti-reflection film is formed on a flat surface of thesemiconductor substrate and laser annealing is performed after theimpurity is introduced into the semiconductor substrate and before thetrench is formed.
 2. In a method of manufacturing a trench gate typefield effect transistor wherein an impurity introduced layer, whichbecomes a source or a drain, is formed by introducing an impurity into asemiconductor substrate, a trench is formed in the impurity introducedlayer, a gate insulating film is formed on a bottom face of the trench,and a gate is formed so as to fill the trench, a method of manufacturinga trench gate type field effect transistor characterized in that laserannealing for activating the impurity is performed after the impurity isintroduced into the semiconductor substrate and before the gate isformed, wherein a flat anti-reflection film is formed on a flat surfaceof the semiconductor substrate and laser annealing is performed afterthe impurity is introduced into the semiconductor substrate and beforethe trench is formed, and a side wall comprising an insulating materialis formed on a side wall of that trench, a second trench is formed in abottom face of said trench with the side wall as a mask, a gateinsulating film is formed on a bottom face of the second trench, and agate is formed so as to fill these trenches.